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Forumas » Mikrovaldikliai » Projektas_JTAG_Digix
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Projektas_JTAG_Digix |
 Parašytas: 2016 12 19, 17:42 |
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Toks kietas Unixistas, o DEC EV7 pamirso...
Kad ir tas pats Z80 turejo duble register bank, kas leido pakankamai efektyviai tvarkytis su daznais pertraukimais (vien persijungiant tarp registru banku). |
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Projektas_JTAG_Digix |
| Parašytas: 2016 12 19, 18:59 |
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| AlgisL rašo: |
| Toks kietas Unixistas, o DEC EV7 pamirso... |
Tais laikais, kai teko UNIX "čiupinėti", jis dar vadinosi ЮНИКС (rusai vengė naudoti UNIX, nes tai keldavo komunistinę santvarką griaunančias aliuzijas - "уних есть операционная система, а что у нас?") ir sukosi ant procesoriaus, kurio pavadinimą dabar nebent užkietėję muziejininkai atsimena: СМ2620. Kuris, savo ruožtu, užėmė visą stalčių, spintų komplekse СМ1600 
O apie DEC EV7 tik dabar sužinojau, bet kai paskaičiau internete, nieko keisto, tai buvo DEC "gulbės giesmė", nepadariusi rinkai jokios ženklesnės įtakos.
| AlgisL rašo: |
Kad ir tas pats Z80 turejo duble register bank, kas leido pakankamai efektyviai tvarkytis su daznais pertraukimais (vien persijungiant tarp registru banku). |
Na va, dabar jau ir pats pripažįsti, kad visai neblogą preemtive multitasking galima ir ant vieno procesoriaus paleisti. Tik kritikai teigia, jog didžiausias Z80 trūkumas - protected memory nebuvimas. Pas Intel tai atsirado nuo 80286. Bet apie ką mes čia diskutuojam?
Skaitau paskaitą apie tai, ką ir pats internete gali rasti |
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Projektas_JTAG_Digix |
| Parašytas: 2016 12 19, 19:11 |
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As dar is tu neisdvesusiu dinozauru, kurie yra mate gyvai veikiancias kolektyvinio naudojimo skaiciavimo masinas "ant K155 serijos", kuriu HDD pakelti reikia minimum dvieju tokiu gerai atsertu dinozauru 
Zilog turejo Z280 ir netgi Z8000 |
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Projektas_JTAG_Digix |
| Parašytas: 2016 12 19, 22:35 |
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Nu gal aš tų dinozaurų...
AlgisL ką siūlai...
Variantas su wait funkcija visai nepatraukus....
Wait, delejų turi nebut, nebent nuėjimas į pertaukimą užima daugiau nei reikia... |
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Projektas_JTAG_Digix |
| Parašytas: 2016 12 19, 23:15 |
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| Ismok skaityti kas parasyta arba perskaityk is naujo. |
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Projektas_JTAG_Digix |
| Parašytas: 2017 03 27, 21:36 |
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Straipsniuką paskaitysiu, bet galvojau tai nieko nedomina....
Gal kas norit prisidėti....
Ten nieko sudėtingo nėra...  |
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Projektas_JTAG_Digix |
| Parašytas: 2017 06 28, 01:25 |
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Šią temą truputi buvau apleidęs, sprendžiau gan sudėtingą problemą.
Turit aparatą ir jame yra Jtag, kaip sužinoti kas prie jo prijungta? |
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Projektas_JTAG_Digix |
| Parašytas: 2017 07 26, 22:32 |
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Toks įspūdis, kad 21 amžius, be jtago negali būti....
Ir vėl jo prireikė, teks užbaigti šį projektą...
Kaip visi žinot TAP kontroleris atrodo sekančiaiL
Kad pasivaikščioti po TAP reikia dviejų signalų, tai TMS ir TCK.
TAP tai 16 padėčių valdymo automatas.
Būseną Test-Logic-Reset, galima pasiekti keliais būdais...
Tai signalu TRST arba TMS =1 ir keli taktiniai signalai TCK 4 ar 5...
Jei bus ir daugiau TCK impulsų, nieko baisaus. Papuolęs į būseną Test-Logic-Reset, išeit iš jos gali tik su TMS=0; |
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Projektas_JTAG_Digix |
| Parašytas: 2017 07 26, 23:10 |
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Yra TAPe du registrai, ar būsenos tai Capture-IR, Capture-DR, pirmame komandos antrame duomenys..
Capture-IR po reseto gali rastis komanda IDCODE arba BYPASS, priklauso nuo įrenginio...
Kadangi Tape viskas veikia SPI principu, tai visą valdymą galimėtų padaryti mygtukų pagalba, tik be drebezgo....
Kadangi jau esam mokyti, tai mygtukais nedarysim...
Pirmiausia pradėsim nuo ID nuskaitymo, kaip tai padaryti?
Tarkim bus Atmega16, tai komanda nuskaityti ID bus IDCODE = 0001 bitais 1 jauniausia. Tai 0001 reikia įrašyti į Capture-IR... , jei pažiūrėsit į TAP diagramą, ten automato nesustabdysi, jis prašoks. Būsenoje Shift-IR sustoja, ji mums ir reikalinga.
Lyrinis nukrypimas:
Kadangi kojos TDI ir TDO turi tuos pačius vardus kaip debugeryje ir device, tai reikia pasitikrinti kuri in kuri out, visko gali būti...
TDI device yra inputas, tai iš Jtago pusės bus outputas.
Tai, kad nuskaityti ID reikia.
Patekti į Shift-IR būseną su TMS ir TCK pagalba, tada TDI ir TCK įrašot komandą, per TDO galit tuo pačiu metu skaityti kokia komanda buvo. Tik nepamiršti, kad paskutinis bitas įsirašo kartu su TMS signalu.
Ir tada einama į Shift-DR būseną, neužeinant į Test-Logic-Reset būseną, nes nuresetins. Shift-DR būsena išstums ID kodą į koją TDO, čia ir paskutinis bitas kartu su TMS signalu....
Pabandysiu papaišyti...
Lyrinis nukrypimas:
Esant būsenose Shift-IR ir Shift-DR stumdyti bitukus galit kiek norit. Shift-IR išeinant liks tik 3+1 paskutiniai. Kituose procesoriuose Capture-IR turi daugiau skilčių. Capture-DR skilčių kiekis priklauso nuo komandos... |
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Projektas_JTAG_Digix |
| Parašytas: 2017 07 29, 11:05 |
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Papaišiau, truputi signalo.
Stumia į vidų ir laukan Data krentančiu frontu, o fiksuojasi kylančiu... |
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Projektas_JTAG_Digix |
| Parašytas: 2017 08 01, 23:36 |
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Gal ir ne viską papaišiau, bet esmę tikriausia supratot...
Atmega16 bsdl failo pvz.
| Kodas: |
------------------------------------------------------------------------
-- A T M E L A V R M I C R O C O N T R O L L E R S --
------------------------------------------------------------------------
-- BSDL file
-- File Name: ATMEGA16.BSD
-- File Revision: 1.2
-- Date created: 2004-10-26
-- Created by: Atmel Corporation
-- Support: avr@atmel.com
--
-- Device: ATmega16
-- rev I
-- Package: 40 pin PDIP
-- 44 pin TQFP (default)
-- 44 pin MLF
--
-- Visit http://www.atmel.com for a updated list of BSDL files.
--
--
------------------------------------------------------------------------
-- Syntax and Semantics are checked against the IEEE 1149.1 standard. --
-- The logical functioning of the standard Boundary-Scan instructions --
-- and of the associated bypass, idcode and boundary-scan register --
-- described in this BSDL file has been verified against its related --
-- silicon by JTAG Technologies B.V. --
------------------------------------------------------------------------
--
-- Notes:
-- 1. The behavior of the Oscillator Boundary Scan cells are dependant
-- on the Oscillator Fuse settings, and are therefore described as
-- "internal".
-- 2. The Boundary Scan cells for controlling the analog features ADC,
-- Comparator and pin pull-ups are described as "internal".
-- Note that this feature is in addition to the (digital) cells on
-- each pin. For information on accessing the pull-up function of the
-- pins, please read the device data sheet.
--
entity ATmega16 is
generic (PHYSICAL_PIN_MAP : string := " TQFP ") ;
port (
RESET : in bit ;
VCC : linkage bit ;
VCC1 : linkage bit ;
VCC2 : linkage bit ;
GND : linkage bit ;
GND1 : linkage bit ;
GND2 : linkage bit ;
GND3 : linkage bit ;
XTAL1 : linkage bit ;
XTAL2 : linkage bit ;
PA : inout bit_vector(0 to 7) ;
PB : inout bit_vector(0 to 7) ;
PC0 : inout bit ;
PC1 : inout bit ;
TCK : in bit ;
TMS : in bit ;
TDO : out bit ;
TDI : in bit ;
PC6 : inout bit ;
PC7 : inout bit ;
PD : inout bit_vector(0 to 7) ;
AREF : linkage bit ;
AVCC : linkage bit
);
use STD_1149_1_1994.all ;
attribute COMPONENT_CONFORMANCE of ATmega16 : entity is
" STD_1149_1_1993 ";
attribute PIN_MAP of ATmega16 : entity is PHYSICAL_PIN_MAP ;
constant PDIP : PIN_MAP_STRING:=
" RESET : 9 , " &
" VCC : 10 , " &
" GND : 11 , " &
" XTAL1 : 13 , " &
" XTAL2 : 12 , " &
" PA : (40,39,38,37,36,35,34,33) , " &
" PB : (1,2,3,4,5,6,7,8) , " &
" PC0 : 22 , " &
" PC1 : 23 , " &
" TCK : 24 , " &
" TMS : 25 , " &
" TDO : 26 , " &
" TDI : 27 , " &
" PC6 : 28 , " &
" PC7 : 29 , " &
" PD : (14,15,16,17,18,19,20,21) , " &
" AREF : 32 , " &
" GND1 : 31 , " &
" AVCC : 30 " ;
constant TQFP : PIN_MAP_STRING:=
" RESET : 4 , " &
" VCC : 5 , " &
" VCC1 : 17 , " &
" VCC2 : 38 , " &
" GND : 6 , " &
" GND1 : 18 , " &
" GND2 : 39 , " &
" XTAL1 : 8 , " &
" XTAL2 : 7 , " &
" PA : (37,36,35,34,33,32,31,30) , " &
" PB : (40,41,42,43,44,1,2,3) , " &
" PC0 : 19 , " &
" PC1 : 20 , " &
" TCK : 21 , " &
" TMS : 22 , " &
" TDO : 23 , " &
" TDI : 24 , " &
" PC6 : 25 , " &
" PC7 : 26 , " &
" PD : (9,10,11,12,13,14,15,16) , " &
" AREF : 29 , " &
" GND3 : 28 , " &
" AVCC : 27 " ;
constant MLF : PIN_MAP_STRING:=
" RESET : 4 , " &
" VCC : 5 , " &
" VCC1 : 17 , " &
" VCC2 : 38 , " &
" GND : 6 , " &
" GND1 : 18 , " &
" GND2 : 39 , " &
" XTAL1 : 8 , " &
" XTAL2 : 7 , " &
" PA : (37,36,35,34,33,32,31,30) , " &
" PB : (40,41,42,43,44,1,2,3) , " &
" PC0 : 19 , " &
" PC1 : 20 , " &
" TCK : 21 , " &
" TMS : 22 , " &
" TDO : 23 , " &
" TDI : 24 , " &
" PC6 : 25 , " &
" PC7 : 26 , " &
" PD : (9,10,11,12,13,14,15,16) , " &
" AREF : 29 , " &
" GND3 : 28 , " &
" AVCC : 27 " ;
attribute TAP_SCAN_IN of TDI : signal is true ;
attribute TAP_SCAN_OUT of TDO : signal is true ;
attribute TAP_SCAN_MODE of TMS : signal is true ;
attribute TAP_SCAN_CLOCK of TCK : signal is (8.0e6, BOTH) ;
attribute INSTRUCTION_LENGTH of ATmega16 : entity is 4 ;
attribute INSTRUCTION_OPCODE of ATmega16 : entity is
" EXTEST ( 0000 )," &
" IDCODE ( 0001 )," &
" SAMPLE ( 0010 )," &
" PRIVATE0 ( 1000 )," &
" PRIVATE1 ( 1001 )," &
" PRIVATE2 ( 1010 )," &
" PRIVATE3 ( 1011 )," &
" AVR_RESET ( 1100 )," &
" BYPASS ( 1111 )" ;
attribute INSTRUCTION_CAPTURE of ATmega16 : entity is " 0001 ";
attribute INSTRUCTION_PRIVATE of ATmega16 : entity is
" PRIVATE0 ," &
" PRIVATE1 ," &
" PRIVATE2 ," &
" PRIVATE3 " ;
attribute IDCODE_REGISTER of ATmega16 : entity is
"1000" &
"1001010000000011" &
"00000011111" &
"1" ;
attribute REGISTER_ACCESS of ATmega16 : entity is
" BOUNDARY ( AVR_RESET )" ;
attribute BOUNDARY_LENGTH of ATmega16 : entity is 141 ;
attribute BOUNDARY_REGISTER of ATmega16 : entity is
-- num cell port func safe [ccell dis rslt]
" 140 ( BC_1 , * , internal , 1 )," &
" 139 ( BC_1 , * , internal , 0 )," &
" 138 ( BC_1 , * , internal , 0 )," &
" 137 ( BC_1 , * , internal , 0 )," &
" 136 ( BC_1 , * , internal , 0 )," &
" 135 ( BC_1 , * , internal , 0 )," &
" 134 ( BC_1 , * , internal , 0 )," &
" 133 ( BC_1 , * , internal , 0 )," &
" 132 ( BC_1 , * , internal , 0 )," &
" 131 ( BC_1 , * , internal , 0 )," &
" 130 ( BC_1 , * , internal , 0 )," &
" 129 ( BC_1 , * , internal , 0 )," &
" 128 ( BC_1 , * , internal , 1 )," &
" 127 ( BC_1 , * , internal , 0 )," &
" 126 ( BC_1 , * , internal , 0 )," &
" 125 ( BC_1 , * , internal , 0 )," &
" 124 ( BC_1 , * , internal , 0 )," &
" 123 ( BC_1 , * , internal , 0 )," &
" 122 ( BC_1 , * , internal , 0 )," &
" 121 ( BC_1 , * , internal , 0 )," &
" 120 ( BC_1 , * , internal , 0 )," &
" 119 ( BC_1 , * , internal , 0 )," &
" 118 ( BC_1 , * , internal , 1 )," &
" 117 ( BC_1 , * , internal , 0 )," &
" 116 ( BC_1 , * , internal , 0 )," &
" 115 ( BC_1 , * , internal , 0 )," &
" 114 ( BC_1 , * , internal , 1 )," &
" 113 ( BC_1 , * , internal , 0 )," &
" 112 ( BC_1 , * , internal , 0 )," &
" 111 ( BC_1 , * , internal , 0 )," &
" 110 ( BC_1 , * , internal , 0 )," &
" 109 ( BC_1 , * , internal , 0 )," &
" 108 ( BC_1 , * , internal , 0 )," &
" 107 ( BC_1 , * , internal , 0 )," &
" 106 ( BC_1 , * , internal , 0 )," &
" 105 ( BC_1 , * , internal , 1 )," &
" 104 ( BC_1 , * , internal , 0 )," &
" 103 ( BC_1 , * , internal , 0 )," &
" 102 ( BC_1 , * , internal , 0 )," &
" 101 ( BC_1 , * , internal , 1 )," &
" 100 ( BC_1 , * , internal , 1 )," &
" 99 ( BC_1 , * , internal , 0 )," &
" 98 ( BC_1 , * , internal , 0 )," &
" 97 ( BC_1 , * , internal , 0 )," &
" 96 ( BC_7 , PB(0) , bidir , X , 95 , 0 , Z )," &
" 95 ( BC_1 , * , control , 0 )," &
" 94 ( BC_1 , * , internal , 0 )," &
" 93 ( BC_7 , PB(1) , bidir , X , 92 , 0 , Z )," &
" 92 ( BC_1 , * , control , 0 )," &
" 91 ( BC_1 , * , internal , 0 )," &
" 90 ( BC_7 , PB(2) , bidir , X , 89 , 0 , Z )," &
" 89 ( BC_1 , * , control , 0 )," &
" 88 ( BC_1 , * , internal , 0 )," &
" 87 ( BC_7 , PB(3) , bidir , X , 86 , 0 , Z )," &
" 86 ( BC_1 , * , control , 0 )," &
" 85 ( BC_1 , * , internal , 0 )," &
" 84 ( BC_7 , PB(4) , bidir , X , 83 , 0 , Z )," &
" 83 ( BC_1 , * , control , 0 )," &
" 82 ( BC_1 , * , internal , 0 )," &
" 81 ( BC_7 , PB(5) , bidir , X , 80 , 0 , Z )," &
" 80 ( BC_1 , * , control , 0 )," &
" 79 ( BC_1 , * , internal , 0 )," &
" 78 ( BC_7 , PB(6) , bidir , X , 77 , 0 , Z )," &
" 77 ( BC_1 , * , control , 0 )," &
" 76 ( BC_1 , * , internal , 0 )," &
" 75 ( BC_7 , PB(7) , bidir , X , 74 , 0 , Z )," &
" 74 ( BC_1 , * , control , 0 )," &
" 73 ( BC_1 , * , internal , 0 )," &
" 72 ( BC_4 , RESET , observe_only , X )," &
" 71 ( BC_4 , * , internal , X )," &
" 70 ( BC_1 , * , internal , X )," &
" 69 ( BC_1 , * , internal , X )," &
" 68 ( BC_1 , * , internal , X )," &
" 67 ( BC_1 , * , internal , X )," &
" 66 ( BC_4 , * , internal , X )," &
" 65 ( BC_4 , * , internal , X )," &
" 64 ( BC_4 , * , internal , X )," &
" 63 ( BC_4 , * , internal , X )," &
" 62 ( BC_1 , * , internal , 0 )," &
" 61 ( BC_7 , PD(0) , bidir , X , 60 , 0 , Z )," &
" 60 ( BC_1 , * , control , 0 )," &
" 59 ( BC_1 , * , internal , 0 )," &
" 58 ( BC_7 , PD(1) , bidir , X , 57 , 0 , Z )," &
" 57 ( BC_1 , * , control , 0 )," &
" 56 ( BC_1 , * , internal , 0 )," &
" 55 ( BC_7 , PD(2) , bidir , X , 54 , 0 , Z )," &
" 54 ( BC_1 , * , control , 0 )," &
" 53 ( BC_1 , * , internal , 0 )," &
" 52 ( BC_7 , PD(3) , bidir , X , 51 , 0 , Z )," &
" 51 ( BC_1 , * , control , 0 )," &
" 50 ( BC_1 , * , internal , 0 )," &
" 49 ( BC_7 , PD(4) , bidir , X , 48 , 0 , Z )," &
" 48 ( BC_1 , * , control , 0 )," &
" 47 ( BC_1 , * , internal , 0 )," &
" 46 ( BC_7 , PD(5) , bidir , X , 45 , 0 , Z )," &
" 45 ( BC_1 , * , control , 0 )," &
" 44 ( BC_1 , * , internal , 0 )," &
" 43 ( BC_7 , PD(6) , bidir , X , 42 , 0 , Z )," &
" 42 ( BC_1 , * , control , 0 )," &
" 41 ( BC_1 , * , internal , 0 )," &
" 40 ( BC_7 , PD(7) , bidir , X , 39 , 0 , Z )," &
" 39 ( BC_1 , * , control , 0 )," &
" 38 ( BC_1 , * , internal , 0 )," &
" 37 ( BC_7 , PC0 , bidir , X , 36 , 0 , Z )," &
" 36 ( BC_1 , * , control , 0 )," &
" 35 ( BC_1 , * , internal , 0 )," &
" 34 ( BC_7 , PC1 , bidir , X , 33 , 0 , Z )," &
" 33 ( BC_1 , * , control , 0 )," &
" 32 ( BC_1 , * , internal , 0 )," &
" 31 ( BC_7 , PC6 , bidir , X , 30 , 0 , Z )," &
" 30 ( BC_1 , * , control , 0 )," &
" 29 ( BC_1 , * , internal , 0 )," &
" 28 ( BC_7 , PC7 , bidir , X , 27 , 0 , Z )," &
" 27 ( BC_1 , * , control , 0 )," &
" 26 ( BC_1 , * , internal , 0 )," &
" 25 ( BC_4 , * , internal , X )," &
" 24 ( BC_1 , * , internal , X )," &
" 23 ( BC_7 , PA(7) , bidir , X , 22 , 0 , Z )," &
" 22 ( BC_1 , * , control , 0 )," &
" 21 ( BC_1 , * , internal , 0 )," &
" 20 ( BC_7 , PA(6) , bidir , X , 19 , 0 , Z )," &
" 19 ( BC_1 , * , control , 0 )," &
" 18 ( BC_1 , * , internal , 0 )," &
" 17 ( BC_7 , PA(5) , bidir , X , 16 , 0 , Z )," &
" 16 ( BC_1 , * , control , 0 )," &
" 15 ( BC_1 , * , internal , 0 )," &
" 14 ( BC_7 , PA(4) , bidir , X , 13 , 0 , Z )," &
" 13 ( BC_1 , * , control , 0 )," &
" 12 ( BC_1 , * , internal , 0 )," &
" 11 ( BC_7 , PA(3) , bidir , X , 10 , 0 , Z )," &
" 10 ( BC_1 , * , control , 0 )," &
" 9 ( BC_1 , * , internal , 0 )," &
" 8 ( BC_7 , PA(2) , bidir , X , 7 , 0 , Z )," &
" 7 ( BC_1 , * , control , 0 )," &
" 6 ( BC_1 , * , internal , 0 )," &
" 5 ( BC_7 , PA(1) , bidir , X , 4 , 0 , Z )," &
" 4 ( BC_1 , * , control , 0 )," &
" 3 ( BC_1 , * , internal , 0 )," &
" 2 ( BC_7 , PA(0) , bidir , X , 1 , 0 , Z )," &
" 1 ( BC_1 , * , control , 0 )," &
" 0 ( BC_1 , * , internal , 0 )" ;
end ATmega16 ;
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Projektas_JTAG_Digix |
| Parašytas: 2017 08 01, 23:53 |
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| Kaip matot, čia gamintojo duotas failas. Ir ten sėdi tokios komandos, kaip private, jos gamintojo nepaaiškintos. Jei dar įvertinus, kad gal būti 16 komandų, o yra tik 9, kas po likusiomis paslėpta.... |
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Projektas_JTAG_Digix |
| Parašytas: 2017 08 02, 13:30 |
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| Tai pavyzdys kaip nereikia programuoti. Programavimo kalbos skirtos zmonems, o ne irenginio registrams. Nebent padarei kazkokia biblioteka bet nori apsunkint priesams gyvenima |
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GTA 6 Wiki
GTA 6 Map,
GTA 6 Characters,
GTA 6 News |
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FS25 Mods
Farming Simulator 25 Mods,
FS25 Maps |
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ATS Trailers
American Truck Simulator Mods,
ATS Trucks,
ATS Maps |
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